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Overview
Comment:Fix the trace output of the OP_Function opcode to show the correct register numbers.
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Timelines: family | ancestors | descendants | both | experimental
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SHA1: 064c283eee82c5053e84058a0e1908e468da6ce3
User & Date: drh 2010-04-07 14:32:11.000
Context
2010-04-07
14:33
Enhance comments on the SrcList object definition to better explain the operation of the SrcList.a[].colUsed field. No changes to code. (check-in: c0f67ea131 user: drh tags: experimental)
14:32
Fix the trace output of the OP_Function opcode to show the correct register numbers. (check-in: 064c283eee user: drh tags: experimental)
2010-04-06
22:33
Veryquick.test is now working. The SQLITE_STMTSTATUS_AUTOINDEX counter added. (check-in: abbf16e5e7 user: drh tags: experimental)
Changes
Unified Diff Show Whitespace Changes Patch
Changes to src/vdbe.c.
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  assert( n==0 || (pOp->p2>0 && pOp->p2+n<=p->nMem+1) );
  assert( pOp->p3<pOp->p2 || pOp->p3>=pOp->p2+n );
  pArg = &aMem[pOp->p2];
  for(i=0; i<n; i++, pArg++){
    apVal[i] = pArg;
    sqlite3VdbeMemStoreType(pArg);
    REGISTER_TRACE(pOp->p2, pArg);
  }

  assert( pOp->p4type==P4_FUNCDEF || pOp->p4type==P4_VDBEFUNC );
  if( pOp->p4type==P4_FUNCDEF ){
    ctx.pFunc = pOp->p4.pFunc;
    ctx.pVdbeFunc = 0;
  }else{








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  assert( n==0 || (pOp->p2>0 && pOp->p2+n<=p->nMem+1) );
  assert( pOp->p3<pOp->p2 || pOp->p3>=pOp->p2+n );
  pArg = &aMem[pOp->p2];
  for(i=0; i<n; i++, pArg++){
    apVal[i] = pArg;
    sqlite3VdbeMemStoreType(pArg);
    REGISTER_TRACE(pOp->p2+i, pArg);
  }

  assert( pOp->p4type==P4_FUNCDEF || pOp->p4type==P4_VDBEFUNC );
  if( pOp->p4type==P4_FUNCDEF ){
    ctx.pFunc = pOp->p4.pFunc;
    ctx.pVdbeFunc = 0;
  }else{
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